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IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
_______________________________________________________________________________________   5
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. V
HVIN
= +48V, C
INBIAS
= 1礔, C
REGOUT
= 2.2礔, R
RTCT
= 25k&, C
RTCT
=
100pF, C
BST
= 0.22礔, V
CSS
= V
CS
= 0V, V
RAMP
= V
DCUVLO
= 3V, T
J
= 0癈 to +125癈, unless otherwise noted. Typical values are at
T
J
= +25癈, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
NIT
SOFT-START (CSS)
Soft-Start Current
I
CSS
V
CSS
 = 0V
33
礎
INTEGRATING FAULT PROTECTION
FLTINT Source Current
I
FLTINT
80
礎
FLTINT Trip Point
V
FLTINT
 rising
2.7
V
FLTINT Hysteresis
0.75
V
INTERNAL POWER FETs
On-Resistance
R
ON POWER
V
DRVIN
 = V
BST
 = 9V,
V
XFRMRH
 = V
SRC
 = 0V, I
DS
 = 50mA
0.4
0.8
&
Off-State Leakage Current
-5
+10
礎
Total Gate Charge Per Power
FET
15
nC
HIGH-SIDE DRIVER
Low to High Latency
t
LH-HS
Driver delay until FET V
GS
 reaches 0.9 x
(V
BST
 - V
XFRMRH
) and is fully on
80
ns
High to Low Latency
t
HL-HS
Driver delay until FET V
GS
 reaches 0.1 x
(V
BST
 - V
XFRMRH
) and is fully off
40
ns
Output Drive Voltage
V
BST
BST to XFRMRH with high side on
8
V
LOW-SIDE DRIVER
Low to High Latency
t
LH-LS
Driver delay until FET V
GS
 reaches 0.9 x
V
DRVIN
 and is fully on
80
ns
High to Low Latency
t
HL-LS
Driver delay until FET V
GS
 reaches 0.1 x
V
DRVIN
 and is fully off
40
ns
CURRENT-LIMIT COMPARATOR (CS)
Current-Limit Threshold
Voltage
V
ILIM
140
156
172
mV
Current-Limit Input Bias
Current
I
BILIM
0 < V
CS
 < 0.3V
-2
+2
礎
Pr
i  n D  l
XFRMRL
t
dILIM
From V
CS
 rising (10mV overdrive) to
V
XFRMRL
 rising
160
ns
BOOST VOLTAGE CIRCUIT (See Figure 9, QB)
Driver Output Delay
t
PPWMD
200
ns
One-Shot Pulse Width
t
PWQB
300
ns
QB R
DSON
Sinking 20mA
30
60
&
THERMAL SHUTDOWN
Shutdown Temperature
T
SH
Temperature rising
+160
癈
Thermal Hysteresis
T
H
20
癈
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